1. Field of the Invention
The present invention relates to a bipolar transistor/insulated gate transistor hybrid semiconductor device which is reduced in size to constitute a Bi-MOS IC or the like.
2. Description of the Related Art
A Bi-MOS IC is known as a bipolar transistor/insulated gate transistor hybrid semiconductor device. In the Bi-MOS IC, both a bipolar element capable of high-speed operation at high frequency and a MOS element adaptable for digital processing and capable of high degree of integration are mounted on the same chip. Various types of circuits can be attained by taking advantage of these elements.
Conventionally, the bipolar element and MOS element are separately formed on their respective diffusion regions on the semiconductor substrate, and a separation region is formed between the diffusion regions. For example, a bias is suitably applied to a first diffusion region on which a bipolar element is formed, a second diffusion region on which a MOS element is formed, and a separation region therebetween so that the regions are connected to each other in a reverse bias state. Since, however, a bias for separating the first and second diffusion regions is applied, a number of wiring layers connecting the separation region and diffusion regions are needed, which prevents a chip from reducing in area.
Assume that a gate array (master slice) including a bipolar element and a MOS element is formed. Actually, the bipolar element and MOS element are hardly used at the same time. Therefore, in the conventional arrangement wherein the bipolar element and MOS element are separately formed in their respective diffusion regions, a degree of use for the elements is remarkably lowered and accordingly a degree of integration is prevented from being enhanced.